1. Field of the Invention
The present invention relates to analog signal multiplier circuits, and in particular, to four-quadrant analog signal multiplier circuits.
2. Description of the Related Art
Referring to FIG. 1, four-quadrant analog signal multiplier circuits, such as that shown, are well known in the art. The two differential analog input signals 11a, 11b are multiplied together with three interconnected differential amplifiers 12, 14, 16 to produce a differential analog output signal 13. One input signal 11b drives the lower differential amplifier 12 which, in turn, drives the upper differential amplifiers 14, 16. This type of amplifier structure is well known in the art. For example, U.S. Pat. No. 4,586,155 (a disclosure of which is incorporated herein by reference) discloses a number of variations of such a circuit.
Referring to FIG. 2, this type of amplifier can also be implemented using metal oxide semiconductor field effect transistors (MOSFETs) interconnected in a similar manner. As with the bipolar junction transistor circuit 10 of FIG. 1, in this MOSFET circuit 20 one input signal 21b drives the lower differential amplifier 22 which, in turn, drives the upper differential amplifiers 24, 26, and the output signal 23 is the product of the two input signals 21a, 21b. This MOSFET implementation is particularly useful for low power applications due to the lower power requirements of MOSFET devices. The overall circuit gain in terms of its transconductance, i.e., its differential output current (I.sub.O(diff) =I.sub.O1 -I.sub.O2 ) as a function of its differential input voltages (V.sub.a, V.sub.b), can be expressed by the following equations (with the various voltages and currents identified as indicated in FIG. 2 and .beta. as transconductance): ##EQU1## Substitute Equations (16)-(19) into (15): ##EQU2## Substitute Equations (10)-(11) into (20): ##EQU3##
This type of circuit, however, does have one characteristic which has become increasingly disadvantageous. Due to their stacked arrangement, i.e., where a pair of differential amplifiers 14/24, 16/26 is effectively stacked upon another differential amplifier 12/22 between the two power supply rails, the dynamic signal range becomes quite limited in a low power applications. In other words, as these types of circuits 10, 20 are required to operate at lower power supply voltages, saturation and/or cutoff of the transistors begins to occur at correspondingly lower signal magnitudes. This requires reduced input in output signal amplitudes, thereby decreasing signal-to-noise ratios.
Referring to FIG. 3, the stacked arrangement of differential amplifiers can be avoided by "folding" what used to be the "lower" differential amplifier 32 such that it is biased between the two power supply rails in a manner similar to what used to be the "upper" differential amplifiers 34, 36. However, while this circuit topography may allow for circuit operation at lower power supply voltages, it does require different types of input devices. Whereas in the stacked amplifier configuration 20 (FIG. 2) the lower differential amplifier 22 used the same types of transistors as the upper differential amplifiers 24, 26 (e.g., N-type MOSFETs), in the folded amplifier configuration 30 (FIG. 3) the folded differential amplifier 32 uses different types of transistors than the output amplifiers 34, 36 (e.g., P-type MOSFETs instead of N-type MOSFETs). This has the disadvantage of making it more difficult to maintain matched input device characteristics and signal gains since, for example, the device characteristics and signal gains of P-type MOSFETs and N-type MOSFETs do not track one another well over variations in device sizes and manufacturing processes.
Accordingly, it would be desirable to have a similarly simple multiplier circuit structure which does not sacrifice performance at reduced signal amplitudes and which provides for more closely matched device characteristics and signal gains.